Mentor Graphics Modelsim SE 10.1c

The system of digital simulation projects based on VHDL, Verilog and "mixed" descriptions with built-in performance analysis, indicating "active" code (code coverage), the comparator time diagrams and visualizer Enhanced Dataflow Window. Main features: high speed simulation for RTL and Gate projects; single simulator kernel and optimized architecture Native Compiled; interactive debugging and analysis with a module Debug Detective; integrated analysis of Code Coverage; optimization of simulation speed by using the Performance Analyzer Performance Analyzer; comprehensive tracing signals Signal Spy; integrated debugger C, C and interfaces support Tcl / Tk; support for OS Unix / Windows / Linux.